As operational requirements increase for electronic structures such as electronic components, e.g., semiconductor chips and modules including same, which mount on circuitized substrates such as chip carriers and printed circuit boards (pcbs) and are coupled together through the substrate's circuitry, so too must the host substrate be able to compensate for same. One particular increase has been the need for higher frequency connections between the mounted components, which connections, as stated, occur through the underlying host substrate. Such connections are subjected to the detrimental effects, e.g., signal deterioration, caused by the inherent characteristics of such known substrate wiring. For example, signal deterioration is expressed in terms of either the“rise time” or the“fall time” of the signal's response to a step change. The deterioration of the signal can be quantified with the formula (Z0*C)/2, where Z0 is the transmission line characteristic impedance, and C is the amount of the via capacitance. In a wire having a typical 50 ohm transmission line impedance, a plated through hole via having a capacitance of 4 pico farad (pf) would represent a 100 pico-second (ps) rise-time (or fall time) degradation, as compared to a 12.5 ps degradation with a 0.5 pf buried via of the invention defined in the afore-mentioned parent application. This difference is significant in systems operation at 800 MHz or faster, where there are associated signal transition rates of 200 ps or faster. The substrates as taught herein are capable of providing signal speeds in the range of at least about 3.0 to about 10.0 gigabits per second (Gb/s), which is indicative of the added complexity needed for such a final structure.
A typical high performance (high speed) substrate such as those used for known chip carriers and multilayered pcbs has not been able to provide wiring densities beyond a certain point due to limitations imposed by the direct current (dc) resistance maximum in connections between components (especially chips). Similarly, high speed signals demand wider lines than normal pcb lines to minimize the“skin effect” losses in long lines. To produce a pcb with all wide lines would be impractical, primarily because of the resulting excessive thickness needed for the final board. Such increased thicknesses are obviously unacceptable from a design standpoint. As exemplified by the examples cited in the patents identified below, various alternative techniques have been used in an attempt to provide such high speed signal handling, but these also typically require unacceptable modifications to the substrate which are not conducive to mass production and/or a product of relatively simple construction. As such, most of these also add to the final cost of the finished product.
As stated, the invention involves circuitized substrates and resulting assemblies which utilize what will be referred to herein as“thru-holes.” These are typically plated (with metallurgy such as copper) openings which extend either partially or entirely through the substrate's thickness for interconnecting various layers and/or components to one another. Each thru-hole may interconnect several such layers and/or components. If located only internally of the multilayered structure, such thru-holes are often referred to simply as“vias”, whereas if these extend a predetermined depth from one or more surfaces of the substrate they are referred to as “blind vias”. If these extend substantially through the entire structure thickness, from one surface to another, these are often referred to in the art as“plated-thru-holes” (pths). By the term“thru-hole” as used herein is meant to include all three types of such openings. From the above description, known substrates including such thru-holes typically suffer from the above mentioned via capacitance-signal degradation problem, which can be greatly amplified if the thru-holes used are of extended length and many signals pass there-over but only for a partial length thereof. See more immediately below.
Yet another signal transmission problem with multilayered circuitized substrates which use thru-holes as part thereof is what is referred to as signal loss due to thru-hole“stub.” Clearly, use of thru-holes of the type defined above is considered essential to provide maximum operational capabilities for the multilayered structure. However, when signals do not pass along the entire length of the thru-hole, e.g., these pass to an internal conductive layer also coupled to the thru-hole but at only a partial depth thereof, there arises a signal“conflict” because part of the signal tends to traverse the remaining length (“stub”) of the thru-hole while another part will pass directly to the internal layer. The result of this“conflict” is signal“noise” or loss, due to the “rebound” of the traversing part of the signal. As explained herein, the invention is able to substantially eliminate such loss.
In U.S. Pat. No. 5,638,287, there are described signal routing circuits (e.g. on printed circuit cards or boards) which allegedly route pulse signals with very short rise times from a lossy driver to multiple devices. In these routing circuits, a complex network of conductors branches from a common junction adjacent the driver output into multiple (in the disclosed embodiment, three) conduction paths of unequal length. In accordance with the invention, the internal impedance of the driver is matched to the aggregate characteristic impedance of the branch paths, and a lossless compensating circuit is attached to a shortest branch path. The compensating circuit is designed to transfer signal reflections of predetermined form to the branching junction at the driver via the shortest branch. Without the compensating circuit, reflections presented to the branching junction from the shortest branch are dissimilar to reflections presented to that junction from other branch paths. Consequently, re-reflections return from the junction to the branches, causing distortions in signals sensed at the devices. However, with the compensating circuit connected in the shortest branch, reflections presented from that branch to the junction appear in a form matching reflections presented by the other branches; and the reflections from all branches then cancel at the driver junction. Consequently, signals sensed at the devices have considerably reduced distortions due to the absence of re-reflections. In a preferred embodiment, the compensating circuit consists of a printed circuit trace of predetermined length (representing a transmission line stub with predetermined phase delay characteristics) in series with a point capacitor (or several point capacitors) having predetermined capacitance (determining the shape of the compensating reflections). The compensating circuit, which extends beyond the end of the shortest branch, connects between the end of that branch and reference potential (e.g. ground). The end of the shortest branch is also attached to a device required to sense signals appearing at that point. A new method and polarized bridge device are disclosed for use in analyzing such networks in particular (and for analyzing transmission line effects in general). This method and device permit precise observation and comparison of reflections produced in branches of a network emanating from a common junction, and accurate determination of compensation suitable for modifying such reflections.
In U.S. Pat. No. 6,084,306, there is described an integrated circuit package having first and second layers, a plurality of routing pads being integral with the first layer, a plurality of upper and lower conduits, respectively, disposed on the upper and lower surfaces of the first layer, one of the upper conduits electrically connected to one of the lower conduits, a plurality of pads disposed on the second layer, vias that electrically connect the pads to the lower conduits and a chip adhered to the second layer having bonding pads, at least one of which is electrically connected to one of the routing pads.
In U.S. Pat. No. 6,353,539, there is described a printed circuit board which includes a first component mounted on a first side of the printed circuit board. A second component has an identical pin-out as the first component. The second component is mounted on a second side of the printed circuit board. A first signal line connects a first land pad coupled to a first contact on the first component with a second land pad coupled to a corresponding first contact on the second component. A second signal line connects a third land pad coupled to a second contact on the first component with a fourth land pad coupled to a corresponding second contact on the second component. The first signal line has is equal in length to the second signal line. This patent discusses different via“stub” length.
In U.S. Pat. No. 6,526,519, there is described an apparatus and method for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.
In U.S. Pat. No. 6,541,712, there is described a multi-layer printed circuit board which includes a via having a conductive upper portion, a conductive lower portion, and an electrically insulating intermediate portion between the upper and lower portions. In one embodiment, the insulating intermediate portion of the via is provided by a non-platable layer of the circuit board, as may be comprised of PTFE. Vias having a continuous conductive coating may be formed through clearance holes in the non-platable layer which are provided with a platable inner surface, either by filling the hole with a platable material, such as epoxy resin, prior to laminating the board or by chemically conditioning the non-platable material to make it platable. In a further embodiment, the insulating intermediate portion of the via has a narrower diameter than the conductive upper and lower portions. This patent discusses elimination of resonant“stub” noise by the plating of only selected portions of the holes in the board and also possibly inserting a conductive“plug” within the hole.
In U.S. Pat. No. 6,545,876, there is described a“technique” for reducing the number of layers in a multilayer circuit board. The multilayer circuit board has a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the board. In one embodiment, the technique is realized by forming a first plurality of electrically conductive vias in the multilayer circuit board extending from the surface of the multilayer circuit board to a first of the plurality of electrically conductive signal layers, wherein the first plurality of electrically conductive vias are arranged so as to form a channel in a second of the plurality of electrically conductive signal layers beneath the first plurality of electrically conductive vias.
In U.S. Pat. No. 6,570,271, there is described an“apparatus” for routing signals to and from at least one circuit component (e.g., to another) that has a plurality of input/output leads and is positioned on the surface of a printed circuit board. This“apparatus” includes a support structure having a first side and a second side, the first side being adapted for having the input/output leads of the circuit component attached thereto. A signal routing strip having a first end and a second end is also included. The first end of the routing strip is configured and adapted to be electrically connected to the input/output leads of the circuit component for transmitting signals to and from the circuit component.
In U.S. Pat. No. 6,601,125, there is described an integrated circuit package for electrically interconnecting a first bus signal path disposed on a printed circuit board and a second bus signal path also disposed on the printed circuit board. The integrated circuit package may have a substrate, an integrated circuit chip die supported by the substrate. The interconnection network may be for electrically connecting the first bus signal path and the second bus signal path to a chip pad on the chip die. Thus, the first bus signal path and the second bus signal path may be electrically interconnected by only the interconnection circuit.
In U.S. Pat. No. 6,608,376, there is described an integrated circuit package that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides at a dielectrically spaced distance between the upper surface and the lower surface. A via extends perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via extends perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors causes the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit
In U.S. Pat. No. 6,662,250, there is described a bus routing strategy for a printed circuit board. The routing strategy ensures that traces coupled to a plurality of synchronous devices are not routed through the center region of each package, ensuring that each trace in a bus is approximately the same length. This apparently serves to minimize the length over which“neck-down” occurs, and ensures that traces are routed without making sharp turns. By using this routing strategy, propagation time differences within each trace group are allegedly minimized. This patent also mentions that the center regions of the printed circuit board under each package are available for vias connected to bypass capacitors.
In U.S. Pat. No. 6,681,338, there are described a method and a system for reducing signal skew caused by dielectric material variations within one or more module substrates. In one embodiment, an elongate module substrate having a long axis includes multiple signal routing layers supported by the module substrate. Multiple devices, such as memory devices (e.g. DRAMs) are supported by the module substrate and are operably connected with the signal routing layers. Multiple skew-reducing locations (e.g. vias) within the module permit signals that are routed in two or more of the multiple signal routing layers to be switched to a different signal routing layer. The skew-reducing locations can be arranged in at least one line that is generally transverse the long axis of the module substrate. The lines of skew-reducing locations can be disposed at various locations on the module. For example, a line of skew-reducing locations can be disposed proximate the middle of the module to effectively offset skew. Multiple skew-reducing locations can be provided at other locations within the module as well so that the signals are switched multiple different times as they propagate through the module.
In U.S. Pat. No. 6,720,501, there is described a multilayer printed circuit board having clustered blind“vias” (a partial depth thru-hole, as explained in greater detail herein-below) in power layers to facilitate the routing of signal traces in signal layers. A portion of the blind vias in the power layers are grouped together to form a cluster of blind vias. Corresponding signal routing channels are provided in the signal layers and aligned with the cluster of blind vias in the power layers to permit routing of signal traces or signal circuitry there-through. A method of manufacturing the multilayered printed circuit board includes assembling a first subassembly of power layers, forming a group of clustered power vias through the first subassembly, assembling a second subassembly of signal layers, combining the first subassembly with the second subassembly such that the clustered vias in the first subassembly align with signal routing channels in the second subassembly, forming signal vias that extend through the first and second subassemblies, and seeding or plating the power and signal vias.
Various other circuitized substrates are described in the following patents:
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The teachings of all of the above documents are incorporated herein by reference.
As understood from the following, a primary purpose of the present invention is to provide an improved circuitized substrate which provides for enhanced high speed connections between electronic components mounted on the substrate by an enhanced signal routing system within the substrate which utilizes the maximum length of the thru-holes and thus substantially eliminates signal loss due to thru-hole“stub.”
It is believed that such a substrate, a method of making same, a multilayered circuitized substrate assembly utilizing two or more such substrates, an electrical assembly using at least one circuitized substrate and having at least one electrical component mounted thereon, and an information handling system using such a substrate (and assemblies) would represent significant advancements in the art.